Serializer/Deserializer (“SERDES”) devices are frequently used in high-speed communication networks to replace slow parallel buses with a single high speed lane. Serial transmission has the advantage of smaller silicon and board foot print and thus a lower cost. While serial data transmission avoids clock and data synchronization problems, some graphic intensive applications require a data link with a higher transmission speed than may be accomplished with purely serial transmission. To provide the desired bandwidth, some approaches recommend a hybrid approach where several serial lanes are bussed together to create a super “serial” link. For these suggested approaches, a system (such as a computer processor and related devices) writes data in parallel to a plurality of data lanes each configured with a First-In First-Out register (“FIFO”). Each write cycle in the FIFO is based on a system clock (“TWC”), and on the read side a SERDES device will read from each parallel FIFO based on a SERDES clock (“XCK”). The TWC and XCK are not always phase aligned, which may result in the transmitted data to be skewed or misaligned when received.
Attempts to eliminate data alignment issues include placing data alignment or data synchronization symbols in each of the parallel data lanes of a serial link. For example, some applications, such as Fibre Channel, encode data using an 8b/10b encoding method prior to transmission. When an 8b/10b encoding method is used, a special “comma” symbol is placed into the data path to align all FIFOs to the same pointer location. However, not all approaches or applications use 8b/10b encoding, and in an application without 8b/10b encoding, a lane deskewing FIFO cannot be used since there is no comma with which to align the data. Accordingly, if a system relying on data alignment of 8b/10b encoded data receives data that is not encoded as such, the system will not function correctly.
An improved method and apparatus for multi-channel synchronization of data is desired.